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Integrated Circuit Systems, Inc.
ICS952011
Programmable Timing Control HubTM for P4TM processor
Recommended Application: SIS 645/645DX/648/650 style chipsets. Output Features: * 2 - Pairs of differential CPUCLKs (differential current mode) * 1 - SDRAM @ 3.3V * 9 - PCI @3.3V (including 2 free-running) * 2 - AGP @ 3.3V * 2 - ZCLKs @ 3.3V * 1- 12/48MHZ @ 3.3V * 1- 24/48MHz, @3.3V selectable by I2C * 3- REF @3.3V, 14.318MHz. Key Specifications: * PCI - PCI output skew: < 500ps * CPU - SDRAM output skew: < 1ns * AGP - AGP output skew: <150ps Features/Benefits: * Selectable asynchronous/synchronous AGP, ZCLK and PCI outputs * Supports DDR333 OEM frequencies * Programmable output frequency, divider ratios, output rise/falltime, output skew. * Programmable spread percentage for EMI control. * Watchdog timer technology to reset system if system malfunctions. * Programmable watch dog safe frequency. * Support I2C Index read/write and block read/write operations. * For PC133 SDRAM system use the ICS9179-16 as the memory buffer. * For DDR SDRAM system use the ICS93735 or ICS93732 as the memory buffer. * Uses external 14.318MHz crystal.
Functionality
Bit2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit5 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit4 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.20 100.20 100.20 100.20 133.60 133.60 133.60 133.60 200.05 200.05 200.05 200.05 166.70 166.70 160.04 166.70 100.20 100.20 100.20 100.20 133.60 133.60 133.60 133.60 200.05 200.05 200.05 200.05 166.70 166.70 160.04 166.70 SDR MHz 100.20 133.60 200.40 167.00 100.20 133.60 200.40 167.00 100.03 133.37 200.05 160.04 100.20 133.36 200.05 166.70 100.20 133.60 200.40 167.00 100.20 133.60 200.40 167.00 100.03 133.37 200.05 160.04 100.20 133.36 200.05 166.70 AGP MHz 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 PCI MHz 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.34 33.34 33.34 33.34 33.40 33.40 33.34 33.34 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.34 33.34 33.34 33.34 33.40 33.40 33.34 33.34 ZCLK MHz 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 133.60 133.60 133.60 133.60 133.60 133.60 133.60 133.60 133.37 133.37 133.37 133.37 133.60 133.60 133.37 133.37
Pin Configuration
VDDREF **FS0/REF0 **FS1/REF1 **FS2/REF2 GNDREF X1 X2 GNDZ ZCLK0 ZCLK1 VDDZ *(PCI_STOP#)PCICLK6 VDDPCI **FS3/PCICLK_F0 **FS4/PCICLK_F1 *MODE0/PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDSDR SDRAM_OUT GND CPU_STOP#(PD#)* CPUCLKT1 CPUCLKC1 VDDCPU GNDCPU CPUCLKT0 CPUCLKC0 IREF GND VDDA SCLK SDATA Vtt_PwrGd/PD#(CPUSTOP#)* GNDAGP AGPCLK0 AGPCLK1 VDDAGP VDD48 12_48MHz/SEL12_48#** 24_48MHz/SEL24_48#*~ GND48
48-SSOP
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This output has 1.5X drive strength
0721A--07/29/03
ICS952011
Integrated Circuit Systems, Inc.
ICS952011
General Description
The ICS952011 is a two chip clock solution for desktop designs using SIS 645/645DX/648/650 style chipsets. When used with a zero delay buffer such as the ICS9179-16 for PC133 or the ICS93735 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952011 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
PLL2 Frequency Dividers 12_48MHz 24_48MHz X1 X2 XTAL REF (2:0) CPUCLKT (1:0) CPUCLKC (1:0) SDRAM_OUT FS (4:0) VTTPWR_GND/PD# CPU_STOP# PCI_STOP# MODE 0 SEL12_48# SEL24_48# Programmable Spread PLL1 Control Logic Programmable Frequency Dividers STOP Logic AGPCLK (1:0) PCICLK (6:0) PCICLKF (1:0) ZCLK (1:0) I REF
Power Groups
Pin Number VDD 1 11 28 29 36 42 48 GND 5 8 25 32 37 41 46 Description REF Output, Crystal Hyper ZCLK outputs 12/24/48MHz, Fix Analog, Fix Digital AGP outputs CPU PLL, CPU Analog, MCLK CPU_T/C outputs SDRAM_Out
0721A--07/29/03
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Integrated Circuit Systems, Inc.
ICS952011
Pin Description
PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 PIN NAME VDDREF **FS0/REF0 **FS1/REF1 **FS2/REF2 GNDREF X1 X2 GNDZ ZCLK0 ZCLK1 VDDZ *(PCI_STOP#)PCICLK6 VDDPCI **FS3/PCICLK_F0 **FS4/PCICLK_F1 *MODE0/PCICLK0 PCICLK1 GNDPCI VDDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 GNDPCI GND48 24_48MHz/SEL24_48#*~ 12_48MHz/SEL12_48#** VDD48 VDDAGP AGPCLK1 AGPCLK0 GNDAGP Vtt_PwrGd/PD#(CPUSTOP #)* SDATA SCLK VDDA GND IREF CPUCLKC0 CPUCLKT0 GNDCPU VDDCPU CPUCLKC1 CPUCLKT1 CPU_STOP#(PD#)* GND SDRAM_OUT VDDSDR PIN TYPE PWR I/O I/O I/O PWR IN OUT PWR OUT OUT PWR I/O PWR I/O I/O I/O OUT PWR PWR OUT OUT OUT OUT PWR PWR I/O I/O PWR PWR OUT OUT PWR I/O I/O IN PWR PWR OUT OUT OUT PWR PWR OUT OUT IN PWR OUT PWR DESCRIPTION Ref, XTAL power supply, nominal 3.3V Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Frequency select latch input pin / 14.318 MHz reference clock. Ground pin for the REF outputs. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin for the ZCLK outputs 3.3V Hyperzip clock output. 3.3V Hyperzip clock output. Power supply for ZCLK clocks, nominal 3.3V Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This input is activated by the MODE selection pin / PCI clock output. Power supply for PCI clocks, nominal 3.3V Frequency select latch input pin / 3.3V PCI free running clock output. Frequency select latch input pin / 3.3V PCI free running clock output. Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / PCI clock output. PCI clock output. Ground pin for the PCI outputs Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. PCI clock output. PCI clock output. Ground pin for the PCI outputs Ground pin for the 48MHz outputs 24MHz/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. 12MHz/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 12MHz. Power pin for the 48MHz output.3.3V Power supply for AGP clocks, nominal 3.3V AGP clock output AGP clock output Ground pin for the AGP outputs This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready to be sampled. This is an active high input. Active low Power Down input or active low CPU_STOP depend on B24b3 IIC selection. Default is PD#. Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant 3.3V power for the PLL core. Ground pin. This pin establishes the reference current for the differential current-mode output pairs. This pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Ground pin for the CPU outputs Supply for CPU clocks, 3.3V nominal "Complimentary" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. "True" clocks of differential pair CPU outputs. These are current mode outputs. External resistors are required for voltage bias. Active low CPU_STOP or Active low Power Down input depend on B24b3 IIC selection. Default is CPU_STOP#. Ground pin. SDRAM seed clock output for external buffer Supply for SDRAM clocks, nominal 3.3V.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor
0721A--07/29/03
3
Integrated Circuit Systems, Inc.
ICS952011
Table 6: CPUCLK Swing Select Functions
Byte 24 Bit 0 MULTSEL0 0 0 0 0 1 1 1 1 Byte 23 Bit 7 MULTSEL1 0 0 1 1 0 0 1 1 Board Target Trace/Term Z 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms 60 ohms 50 ohms Reference R, Iref = Vdd/(3*Rr) Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 475 1% Iref = 2.32mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Rr = 221 1% Iref = 5mA Output Current Ioh = 5*Iref Ioh = 5*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 7*Iref Ioh = 7*Iref Voh @ Z, Iref=2.32mA 0.71V @ 60 0.59V @ 50 0.56V @ 60 0.47V @ 50 0.85V /2 60 0.71V @ 50 0.99V @ 60 0.82V @ 50
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv) 30 (DC equiv) 25 (DC equiv)
Ioh = 5*Iref Ioh = 5*Iref Ioh = 4*Iref Ioh = 4*Iref Ioh = 6*Iref Ioh = 6*Iref Ioh = 7*Iref Ioh = 7*Iref
0.75V @ 30 0.62V @ 20 0.60 @ 20 0.5V @ 20 0.90V @ 30 0.75V @ 20 1.05V @ 30 0.84V @ 20
0721A--07/29/03
4
Integrated Circuit Systems, Inc.
ICS952011
General I2C serial interface information for the ICS952011 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P Not acknowledge stoP bit
0721A--07/29/03
5
Integrated Circuit Systems, Inc.
ICS952011
Table1: QuadRom Frequency Selection Table
B24 Bit6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B24 Bit5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit5 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit4 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.20 100.20 100.20 100.20 133.60 133.60 133.60 133.60 200.05 200.05 200.05 200.05 166.70 166.70 160.04 166.70 100.20 100.20 100.20 100.20 133.60 133.60 133.60 133.60 200.05 200.05 200.05 200.05 166.70 166.70 160.04 166.70 SDR MHz 100.20 133.60 200.40 167.00 100.20 133.60 200.40 167.00 100.03 133.37 200.05 160.04 100.20 133.36 200.05 166.70 100.20 133.60 200.40 167.00 100.20 133.60 200.40 167.00 100.03 133.37 200.05 160.04 100.20 133.36 200.05 166.70 AGP MHz 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 PCI MHz 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.34 33.34 33.34 33.34 33.40 33.40 33.34 33.34 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.34 33.34 33.34 33.34 33.40 33.40 33.34 33.34 ZCLK MHz 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 133.60 133.60 133.60 133.60 133.60 133.60 133.60 133.60 133.37 133.37 133.37 133.37 133.60 133.60 133.37 133.37
0721A--07/29/03
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Integrated Circuit Systems, Inc.
ICS952011
Table1: QuadRom Frequency Selection Table (Continued)
B24 Bit6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B24 Bit5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 200.00 200.00 200.00 200.00 166.66 166.67 160.00 166.67 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 200.00 200.00 200.00 200.00 166.66 166.67 160.00 166.67 SDR MHz 100.00 133.33 200.00 166.67 100.00 133.33 200.00 166.67 100.00 133.33 200.00 160.00 100.00 133.33 200.00 166.67 100.00 133.33 200.00 166.67 100.00 133.33 200.00 166.67 100.00 133.33 200.00 160.00 100.00 133.33 200.00 166.67 AGP MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 ZCLK MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33 133.33
0721A--07/29/03
7
Integrated Circuit Systems, Inc.
ICS952011
Table1: QuadRom Frequency Selection Table (Continued)
B24 Bit6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B24 Bit5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.20 100.20 100.20 100.20 133.60 133.60 133.60 133.60 200.05 200.05 200.05 200.05 166.70 166.70 160.04 166.70 100.20 100.20 100.20 100.20 133.60 133.60 133.60 133.60 200.05 200.05 200.05 200.05 166.70 166.70 160.04 166.70 SDR MHz 100.20 133.60 200.40 167.00 100.20 133.60 200.40 167.00 100.03 133.37 200.05 160.04 100.20 133.36 200.05 166.70 100.20 133.60 200.40 167.00 100.20 133.60 200.40 167.00 100.03 133.37 200.05 160.04 100.20 133.36 200.05 166.70 AGP MHz 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.80 66.68 66.68 66.68 66.68 66.68 66.80 66.68 66.68 PCI MHz 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.34 33.34 33.34 33.34 33.40 33.40 33.34 33.34 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.40 33.34 33.34 33.34 33.34 33.40 33.40 33.34 33.34 ZCLK MHz 80.16 80.16 80.16 80.16 80.16 80.16 80.16 80.16 80.02 80.02 80.02 80.02 80.16 80.16 80.02 80.02 100.20 100.20 100.20 100.20 100.20 100.20 100.20 100.20 100.03 100.03 100.03 100.03 100.20 100.20 100.03 100.03
0721A--07/29/03
8
Integrated Circuit Systems, Inc.
ICS952011
Table1: QuadRom Frequency Selection Table (Continued)
B24 Bit6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 B24 Bit5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit4 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 200.00 200.00 200.00 200.00 166.66 166.67 160.00 166.67 100.00 100.00 100.00 100.00 133.33 133.33 133.33 133.33 200.00 200.00 200.00 200.00 166.66 166.67 160.00 166.67 SDR MHz 100.00 133.33 200.00 166.67 100.00 133.33 200.00 166.67 100.00 133.33 200.00 160.00 100.00 133.33 200.00 166.67 100.00 133.33 200.00 166.67 100.00 133.33 200.00 166.67 100.00 133.33 200.00 160.00 100.00 133.33 200.00 166.67 AGP MHz 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 66.66 PCI MHz 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 33.33 ZCLK MHz 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 80.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00
0721A--07/29/03
9
Integrated Circuit Systems, Inc.
ICS952011
I2C Table: Function Control Register
Byte 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PDEN AZCLKFS WDS_EN PCICLK6 AZCLKFS Reserved AEN1 AEN0 Control Function PD# Enable Async Zclk Freq Select in N-programming (Mode 01, see table 3) WD Soft Enable Output Control Async Zclk Freq Select (Mode 10 & 11, see table 3) Reserved Zclk/Agp/Pci Freq Source Select Control Type RW RW RW RW RW RW RW RW 0 Disable 66.6MHz Disable Disable 66MHz See Table 3 : ZCLK, AGP & PCI Frequency Source Decode Table 1 Enable 133.3MHz Enable Enable 132MHz PWD 1 1 1 1 1 1 0 0
Table 3: ZCLK Frequency Source Decode Table
Byte0 Bit1 0 0 1 1 Byte0 Bit0 0 1 0 1 ZCLK & AGP & PCI See Table 1, QuadRom Frequency Table N-Programming for ZCLK/AGP/PCI See Table 1 for AGP/PCI, B0b3 for ZCLK freq N-Prog for AGP/PCI, B0b3 for ZCLK freq
I2C Table: Async N-Programming Frequency Select Register
Byte 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N PLL3 Div7 N PLL3 Div6 N PLL3 Div5 N PLL3 Div4 N PLL3 Div3 N PLL3 Div2 N PLL3 Div1 N PLL3 Div0 Control Function The decimal representation of N PLL2 Div (7:0) + 8 is equal to VCO divider value for PLL2. Default at power up = 66.67MHz Type RW RW RW RW RW RW RW RW 0 1 PWD 0 1 0 0 0 1 1 1
I2C Table: Reserved Register
Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 1 1 1 1 1 1
0721A--07/29/03
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Integrated Circuit Systems, Inc.
ICS952011
Byte1 (7:0) Hex 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B
VCO Freq 360.34 361.53 362.73 363.92 365.11 366.31 367.50 368.69 369.89 371.08 372.27 373.47 374.66 375.85 377.05 378.24 379.43 380.62 381.82 383.01 384.20 385.40 386.59 387.78 388.98 390.17 391.36 392.56 393.75 394.94 396.14 397.33 398.52 399.72 400.91 402.10 403.30 404.49
AGP Freq 60.06 60.26 60.45 60.65 60.85 61.05 61.25 61.45 61.65 61.85 62.05 62.24 62.44 62.64 62.84 63.04 63.24 63.44 63.64 63.84 64.03 64.23 64.43 64.63 64.83 65.03 65.23 65.43 65.62 65.82 66.02 66.22 66.42 66.62 66.82 67.02 67.22 67.41
PCI Freq 30.03 30.13 30.23 30.33 30.43 30.53 30.62 30.72 30.82 30.92 31.02 31.12 31.22 31.32 31.42 31.52 31.62 31.72 31.82 31.92 32.02 32.12 32.22 32.32 32.41 32.51 32.61 32.71 32.81 32.91 33.01 33.11 33.21 33.31 33.41 33.51 33.61 33.71
Byte1 (7:0) Hex 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71
VCO Freq 405.68 406.87 408.07 409.26 410.45 411.65 412.84 414.03 415.23 416.42 417.61 418.81 420.00 421.19 422.39 423.58 424.77 425.97 427.16 428.35 429.55 430.74 431.93 433.12 434.32 435.51 436.70 437.90 439.09 440.28 441.48 442.67 443.86 445.06 446.25 447.44 448.64 449.83
AGP Freq 67.61 67.81 68.01 68.21 68.41 68.61 68.81 69.01 69.20 69.40 69.60 69.80 70.00 70.20 70.40 70.60 70.80 70.99 71.19 71.39 71.59 71.79 71.99 72.19 72.39 72.59 72.78 72.98 73.18 73.38 73.58 73.78 73.98 74.18 74.37 74.57 74.77 74.97
PCI Freq 33.81 33.91 34.01 34.11 34.20 34.30 34.40 34.50 34.60 34.70 34.80 34.90 35.00 35.10 35.20 35.30 35.40 35.50 35.60 35.70 35.80 35.89 35.99 36.09 36.19 36.29 36.39 36.49 36.59 36.69 36.79 36.89 36.99 37.09 37.19 37.29 37.39 37.49
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Byte1 (7:0) Hex 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97
VCO Freq 451.02 452.22 453.41 454.60 455.80 456.99 458.18 459.37 460.57 461.76 462.95 464.15 465.34 466.53 467.73 468.92 470.11 471.31 472.50 473.69 474.89 476.08 477.27 478.47 479.66 480.85 482.05 483.24 484.43 485.62 486.82 488.01 489.20 490.40 491.59 492.78 493.98 495.17
AGP Freq 75.17 75.37 75.57 75.77 75.97 76.16 76.36 76.56 76.76 76.96 77.16 77.36 77.56 77.76 77.95 78.15 78.35 78.55 78.75 78.95 79.15 79.35 79.55 79.74 79.94 80.14 80.34 80.54 80.74 80.94 81.14 81.34 81.53 81.73 81.93 82.13 82.33 82.53
PCI Freq 37.59 37.68 37.78 37.88 37.98 38.08 38.18 38.28 38.38 38.48 38.58 38.68 38.78 38.88 38.98 39.08 39.18 39.28 39.37 39.47 39.57 39.67 39.77 39.87 39.97 40.07 40.17 40.27 40.37 40.47 40.57 40.67 40.77 40.87 40.97 41.07 41.16 41.26
Byte1 (7:0) Hex 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD
VCO Freq AGP Freq 496.36 497.56 498.75 499.94 501.14 502.33 503.52 504.72 505.91 507.10 508.30 509.49 510.68 511.87 513.07 514.26 515.45 516.65 517.84 519.03 520.23 521.42 522.61 523.81 525.00 526.19 527.39 528.58 529.77 530.97 532.16 533.35 534.55 535.74 536.93 538.12 539.32 540.51 82.73 82.93 83.12 83.32 83.52 83.72 83.92 84.12 84.32 84.52 84.72 84.91 85.11 85.31 85.51 85.71 85.91 86.11 86.31 86.51 86.70 86.90 87.10 87.30 87.50 87.70 87.90 88.10 88.30 88.49 88.69 88.89 89.09 89.29 89.49 89.69 89.89 90.09
PCI Freq 41.36 41.46 41.56 41.66 41.76 41.86 41.96 42.06 42.16 42.26 42.36 42.46 42.56 42.66 42.76 42.86 42.95 43.05 43.15 43.25 43.35 43.45 43.55 43.65 43.75 43.85 43.95 44.05 44.15 44.25 44.35 44.45 44.55 44.64 44.74 44.84 44.94 45.04
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I2C Table: Reserved Register
Byte 3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 1 1 1 1 1 1
I2C Table: Frequency Select Register
Byte 4 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name FS3 FS2 FS1 FS0 FS Source FS4 SS_EN Outputs Control Function Freq Select Bit 7 Freq Select Bit 6 Freq Select Bit 5 Freq Select Bit 4 Frequency HW/IIC Select Freq Select Bit 2 Spread Enable Output Control Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 1 0
See Table1 : Quad Rom Frequency Selection Table Latch Input IIC
See Table1 OFF ON Running Tri-state
I2C Table: Read Back Register
Byte 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name WDHRB WDSRB MULTISEL FS4RB FS3RB FS2RB FS1RB FS0RB Control Function WD Hard Alarm Status Read back WD Soft Alarm Status Read back Multisel Read back FS4 Read back FS3 Read back FS2 Read back FS1 Read back FS0 Read back Type R R R R R R R R 0 Normal Normal 1 Alarm Alarm PWD X X X X X X X X
I2C Table: Output Control Register
Byte 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 10 9 14 15 40, 39 44, 43 40, 39 44, 43 Pin # Name ZCLK_1 ZCLK_0 PCI_F0 PCI_F1 CPUT0/C0 CPUT1/C1 CPUT0/C0 CPUT1/C1 Control Function Output Control Output Control PCI_STOP# Control PCI_STOP# Control CPU_STOP# Control CPU_STOP# Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Stop Disable Stop Disable Stop Disable Stop Disable Disable Disable 1 Enable Enable Stop Enable Stop Enable Stop Enable Stop Enable Enable Enable PWD 1 1 0 0 1 1 1 1
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I2C Table: Output Control Register
Byte 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 15 14 23 22 21 20 17 16 Pin # Name PCICLK_F1 PCICLK_F0 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0 Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable Disable Disable Disable Disable Disable 1 Enable Enable Enable Enable Enable Enable Enable Enable PWD 1 1 1 1 1 1 1 1
I2C Table: Byte Count Register
Byte 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 1 1 1 1
Writing to this register will configure how many bytes will be read back, default is 0F = 15 bytes.
I2C Table: Watchdog Timer Register
Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name WD7 WD6 WD5 WD4 WD3 WD2 WD1 WD0 Control Function These bits represent X*290ms the watchdog timer will wait before it goes to alarm mode. Default is 16 X 290ms =4.64 seconds Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 1 0 0 0 0
I2C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name M/NEN WDEN Reserved WD SF4 WD SF3 WD SF2 WD SF1 WD SF0 Control Function M/N Programming Enable Watchdog Enable Reserved Writing to these bit will configure the safe frequency as Byte4bit 2, (7:4) Type RW R RW RW RW RW RW RW 0 Disable Disable 1 Enable Enable PWD 0 0 0 0 0 0 0 1
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I2C Table: VCO Frequency Control Register
Byte 11 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div8 M Div6 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Bit 8 The decimal representation of M Div (6:0) + 2 is equal to reference divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
I2C Table: VCO Frequency Control Register
Byte 12 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0 Control Function The decimal representation of N Div (8:0) + 8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
I2C Table: Spread Spectrum Control Register
Byte 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0 Control Function These Spread Spectrum bits will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
I2C Table: Spread Spectrum Control Register
Byte 14 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Reserved Reserved It is recommended to use ICS Spread % table for spread programming. Type R R RW RW RW RW RW RW 0 1 PWD 0 0 X X X X X X
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I2C Table: Output Divider Control Register
Byte 15 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name SDDiv3 SDDiv2 SDDiv1 SDDiv0 CPU Div3 CPU Div2 CPU Div1 CPU Div0 Control Function SD divider ratio can be configured via these 4 bits individually. CPU divider ratio can be configured via these 4 bits individually. Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
See Table 4: Divider Ratio Combination Table
See Table 4: Divider Ratio Combination Table
Table 4: CPU, SDR Divider Ratio Combination Table
Divider (3:2) Bit Divider (1:0) 00 01 10 11 LSB 00 0000 0001 0010 0011 Address 1 2 3 5 7 Div 01 0100 0101 0110 0111 Address 2 4 6 10 14 Div 10 1000 1001 1010 1011 Address 4 8 12 20 28 Div 11 1100 1101 1110 1111 Address MSB 8 16 24 40 56 Div
I2C Table: Output Divider Control Register
Byte 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD X X X X X X X X
I2C Table: Output Divider Control Register
Byte 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name Reserved Reserved SDINV CPUINV Reserved Reserved Reserved Reserved Control Function Reserved Reserved SD Phase Invert CPU Phase Invert Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 Default Default 1 Inverse Inverse PWD X X X X X X X X
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Integrated Circuit Systems, Inc.
ICS952011
I2C Table: Group Skew Control Register
Byte 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name CPUSkw1 CPUSkw0 SDSkw1 SDSkw0 Reserved Reserved Reserved Reserved Control Function CPU-CPU Skew Control CPU-SD Skew Control Reserved Reserved Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 1 1 0 0 1 0 0 0
See Table 5: 4-Steps Skew Programming Table See Table 5: 4-Steps Skew Programming Table -
I2C Table: Group Skew Control Register
Byte 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name ZCLKSkw1 ZCLKSkw0 Reserved Reserved AGPSkw1 AGPSkw0 Reserved Reserved Control Function CPU-ZCLK Skew Control Reserved Reserved CPU-AGP Skew Control Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 0
See Table 5: 4-Steps Skew Programming Table See Table 5: 4-Steps Skew Programming Table -
I2C Table: Group Skew Control Register
Byte 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name PCI_FSkw1 PCI_FSkw0 Reserved Reserved PCISkw1 PCISkw0 Reserved Reserved Control Function CPU-PCI_F Skew Control Reserved Reserved CPU-PCI Skew Control Reserved Reserved Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 0
See Table 5: 4-Steps Skew Programming Table See Table 5: 4-Steps Skew Programming Table -
Table 5: 4-Steps Skew Programming Table
4 Step 0 1 MSB 0 0ps 500ps 1 250ps 750ps LSB -
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I2C Table: Slew Rate Control Register
Byte 21 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin # Name 24/48Slw1 24/48Slw0 AGPSlw1 AGPSlw0 ZCLKSlw1 ZCLKSlw0 REFSlw1 REFSlw0 Control Function 24/48 Slew Rate Control AGP Slew Rate Control ZCLK Slew Rate Control REF Slew Rate Control Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 0
I2C Table: Slew Rate Control Register
Byte 22 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 30 31 Pin # Name SDSlw1 SDSlw0 AGPCLK1 AGPCLK0 PCI_FSlw1 PCI_FSlw0 PCISlw1 PCISlw0 Control Function SD Slew Rate Control Output Control Output Control PCI_F Slew Rate Control PCI Slew Rate Control Type RW RW RW RW RW RW RW RW 0 Disable Disable 1 Enable Enable PWD 0 0 1 1 0 0 0 0
I2C Table: Output Control Register
Byte 23 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 26 47 27 26 4 3 2 Pin # Name MultSel1 SEL24_48 SDRAM_OUT 12_48MHz 24_48MHz REF2 REF1 REF0 Control Function IREF X plier Control 24MHz or 48MHz Output Control Output Control Output Control Output Control Output Control Output Control Type RW RW RW RW RW RW RW RW 0 See Table 6 48MHz Disable Disable Disable Disable Disable Disable 24MHz Enable Enable Enable Enable Enable Enable 1 PWD 0 1 1 1 1 1 1 1
I2C Table: Output Control Register
Byte 24 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 27 45,33 Pin # Name SEL12_48 FS6 FS5 Reserved STOP_PD Swap SS_SEL SS_SEL MultSel0 Control Function 12MHz or 48MHz Freq Select bit 6 Freq Select bit 5 Reserved Swap CPU_STOP# and PD# location SS Scheme Select1 SS Scheme Select1 IREF X plier Control Type RW RW RW RW RW RW RW RW 0 48MHz 1 12MHz PWD 0 0 0 0 1 0 0 1
See Table 1 Stop-Pin33 Stop-Pin45 PD#-Pin45 PD#-Pin33 See Table 2: Spread Spectrum Selection Table See Table 6: MultSel Selection Table
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Table2: Spread Spectrum Select Table
SS1 (Byte 24 bit 2) 0 0 1 1 SS0 (Byte 24 bit 1) 0 1 0 1 QuadRom Sec1&3 b(6:5,FS3 Byte4:bit7) = 000, 100 OFF OFF 0.22% 0.48% QuadRom Sec1&3 b(6:5,FS3 Byte4:bit7) = 001, 101 0.35% 0.50% 0.75% 1.00% QuadRom Sec2&4 b(6:3) = 0011 0.40% 0.55% 0.80% 1.00%
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ICS952011
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND -0.5 V to VDD +0.5 V 0C to +70C -65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% (unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency SYMBOL CONDITIONS VIH VIL IIH VIN = VDD IIL1 VIN = 0 V; Inputs with no pull-up resistors IIL2 VIN = 0 V; Inputs with pull-up resistors IDD(op) IDDPD CL = 0 pF; Select @ 100MHz CL = 0 pF; With input address to VDD or GND VDD = 3.3 V MIN 2 VSS - 0.3 -5 -200 213 15 11 27 1.8 1 2.19 TYP MAX UNITS VDD + 0.3 V 0.8 V 5 A A A 280 40 16 5 45 3 3 4 mA mA MHz pF pF ms ms ns
Fi CIN Logic Inputs 1 Input Capacitance CINX X1 & X2 pins 1 Ttrans To 1st crossing of target Freq. Transition Time 1 TSTAB From VDD = 3.3 V to 1% target Freq. Clk Stabilization 1 TCPU-PCI VT = 1.5 V Skew 1 Guaranteed by design, not 100% tested in production.
1.5
Electrical Characteristics - PCICLK
TA = 0 - 70C; VDD = 3.3 V,+/-5%; CL = 30 pF PARAMETER SYMBOL CONDITIONS IOH = -18 mA Output High Voltage VOH1 IOL = 9.4 mA Output Low Voltage VOL1 VOH = 2.0 V Output High Current IOH1 VOL = 0.8 V Output Low Current IOL1 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V Fall Time1 tf1 VOH = 2.4 V, VOL = 0.4 V 1 Duty Cycle dt1 VT = 1.5 V Skew1 tsk1 VT = 1.5 V VT = 1.5 V tjcyc-cyc1 Jitter
1
MIN 2.1
TYP
MAX 0.4 -22 57 2 2 55 500 500
16 1.96 1.95 51.6 70 100
45
UNITS V V mA mA ns ns % ps ps
Guaranteed by design, not 100% tested in production.
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Electrical Characteristics - CPUCLKT/C
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 757 9 775 -3 386 42 300 280 850 150 1150 550 140 700 700 125 125 55 100 150 mV mV mV mV ps ps ps ps % ps ps
Current Source VO = Vx 3000 Zo1 Output Impedance Statistical measurement on single ended Voltage High VHigh 660 signal using oscilloscope math function. VLow -150 Voltage Low Measurement on single ended signal using Max Voltage Vovs absolute value. Vuds -450 Min Voltage Crossing Voltage Vcross(abs) 250 (abs) Crossing Voltage d-Vcross Variation of crossing over all edges (var) VOL = 0.175V, VOH = 0.525V tr 175 Rise Time tf VOH = 0.525V VOL = 0.175V Fall Time 175 d-tr Rise Time Variation d-tf Fall Time Variation Duty Cycle Skew Jitter, Cycle to cycle dt3 tsk3 tjcyc-cyc1 Measurement from differential wavefrom VT = 50% VT = 50% 45
50 32 43
Electrical Characteristics - ZCLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance RDSP11 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA 1 Output Low Voltage VOL IOL = 1 mA V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH1 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V Duty Cycle dt11 1 VT = 1.5 V Skew tsk1 VT = 1.5 V 3V66 tjcyc-cyc1 Jitter MIN 12 2.4 -33 30 0.5 0.5 45 TYP MAX 55 0.55 -33 38 2 2 55 250 250 UNITS MHz V V mA mA ns ns % ps ps
1.36 1.37 52.3 15 201
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Integrated Circuit Systems, Inc.
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Electrical Characteristics - AGPCLK
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-30 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS Output Frequency FO1 Output Impedance RDSP11 VO = VDD*(0.5) 1 Output High Voltage VOH IOH = -1 mA Output Low Voltage VOL1 IOL = 1 mA 1 V OH@MIN = 1.0 V, V OH@MAX = 3.135 V Output High Current IOH 1 VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Output Low Current IOL 1 Rise Time tr1 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf1 VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V Duty Cycle dt11 1 VT = 1.5 V Skew tsk1 VT = 1.5 V 3V66 tjcyc-cyc1 Jitter MIN 12 2.4 -33 30 0.5 0.5 45 TYP MAX 55 0.55 -33 38 2 2 55 250 250 UNITS MHz V V mA mA ns ns % ps ps
1.83 1.69 52.7 32 240
Electrical Characteristics - 12_48MHz, 24_48MHz
TA = 0 - 70C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified) PARAMETER SYMBOL CONDITIONS 1 VO = VDD*(0.5) Output Impedance RDSP1 1 IOH = -1 mA Output High Voltage VOH 1 IOL = 1 mA Output Low Voltage VOL V OH@MIN = 1.0 V Output High Current IOH1 V OH@MAX = 3.135 V VOL @MIN = 1.95 V Output Low Current IOL1 VOL @MAX = 0.4 V VOL = 0.4 V, VOH = 2.4 V Rise Time tr11 1 VOH = 2.4 V, VOL = 0.4 V Fall Time tf1 1 VT = 1.5 V Duty Cycle dt1 Jitter
1
MIN 20 2.4 -29
TYP
MAX 60 0.4 -23
UNITS V V mA mA ns ns % ps
29 0.5 0.5 45 1.27 1.4 52.7 268 27 1 1 55 350
tjcyc-cyc1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - REF
TA = 0 - 70C; VDD = 3.3 V , +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -12 mA Output High Voltage VOH5 Output Low Voltage VOL5 IOL = 9 mA Output High Current IOH5 VOH = 2.0 V Output Low Current IOL5 VOL = 0.8 V Rise Time1 tr5 VOL = 0.4 V, VOH = 2.4 V 1 Fall Time tf5 VOH = 2.4 V, VOL = 0.4 V Duty Cycle1 dt5 VT = 1.5 V 1 tjcyc-cyc5 VT = 1.5 V Jitter MIN 2.6 TYP UNITS V 0.4 V -22 mA mA 4 ns 4 ns 55 % 1000 ps MAX
16 1.98 1.87 54.2 213
45
0721A--07/29/03
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Integrated Circuit Systems, Inc.
ICS952011
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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Integrated Circuit Systems, Inc.
ICS952011
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
Assertion of PCI_STOP# Waveforms
PCI_STOP# PCI_F 33MHz PCI 33MHz
tsu
CPU_STOP# - Assertion (transition from logic "1" to logic "0") The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I2C configuration to be stoppable via assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown. The final state of the stopped CPU signals is CPUT=Low and CPUC=High. There is to be no change to the output drive current values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven. Assertion of CPU_STOP# Waveforms
CPU_STOP# CPUT CPUC
CPU_STOP# Functionality
CPU_STOP# 1 0
CPUT Normal iref * Mult
CPUC Normal Float
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Integrated Circuit Systems, Inc.
ICS952011
N
c
L
E1 INDEX AREA
E
12 h x 45 D
A A1
In Millimeters SYMBOL COMMON DIMENSIONS MIN MAX A 2.41 2.80 A1 0.20 0.40 b 0.20 0.34 c 0.13 0.25 D SEE VARIATIONS E 10.03 10.68 E1 7.40 7.60 e 0.635 BASIC h 0.38 0.64 L 0.50 1.02 N SEE VARIATIONS 0 8 VARIATIONS N 48
10-0034
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
D mm. MIN 15.75 MAX 16.00 MIN .620
D (inch) MAX .630
Ref erence Doc.: JEDEC Publicat ion 95, M O-118
Ordering Information
ICS952011yFT
Example:
ICS XXXXXX y F - T
Designation for tape and reel packaging Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0721A--07/29/03
25

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